1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming field effect transistors (FETs) and at least a portion of a non-FET circuit element on a semiconductor-on-insulator (SOI) substrate.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, ASICs, storage devices and the like, a very large number of circuit elements, e.g., field effect transistors (FETs), bi-polar transistor devices, junction field effect transistors (JFETs), capacitors, resistors, etc., are formed in and on a restricted chip area. As used herein and in the attached claims, the term “FET device” will refer to devices that have a structure corresponding to that of devices that were once known as MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). Of course, the materials of construction and the configurations of such FET devices have changed over time and when reference is made to such devices, the person skilled in the art will appreciate that such reference does not imply any type of limitation as to the materials of construction and/or the particular configurations of such devices. For example, FET devices come in a variety of different configurations, e.g., planar devices, FinFET devices, omega gate devices, gate-all-around (GAA) devices, such as nanowire devices, etc., and they may be formed with polysilicon gate electrodes or gate electrodes comprised of one or more layers of metal. The FET devices may be manufactured using so-called replacement-gate or “gate-first” manufacturing techniques. Irrespective of their precise form or configuration, these FET devices are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of a field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region that forms in the semiconductor substrate under the gate electrode between a drain region and a source region. A layer of insulating material separates the gate electrode from the semiconductor substrate.
In contrast to FET devices, integrated circuits may also include other types of non-FET circuit elements such as, for example, horizontal and vertical bipolar transistor devices, junction field effect transistors (JFETs), capacitors, resistors, diodes, well contacts or well taps, etc. As used herein and in the claims, the term a “non-FET circuit element” means any type of circuit element that is not a FET device. Many current day integrated circuit products include both FET devices and non-FET circuit elements. For example, some IC products include fully depleted or partially depleted FETs, as well as non-FET circuit elements, such as bipolar transistors. These IC products are sometimes formed on so-called SOI substrates (Semiconductor-On-Insulator substrates). However, the formation of both FET devices and non-FET circuit elements on an SOI substrate is not without problems.
FIG. 1A depicts an illustrative SOI substrate 12 wherein a FET device will be formed in a FET region of the substrate 12 and a non-FET circuit element will be formed in a non-FET region of the substrate 12. In general, the SOI substrate 12 is comprised of an active semiconductor layer 12A, a bulk semiconductor layer 12C and a buried insulation layer 12B (sometimes referred to as a “BOX” layer) positioned between the active layer 12A and the bulk layer 12C. The FET device will be formed in and above the active layer 12A in the FET region, while the non-FET circuit element will be formed in and above the bulk layer 12C in the non-FET region of the substrate 12. The thickness of the active layer 12A may vary depending upon whether or not the FET device is intended to be a fully depleted device or a partially depleted device. The techniques used to form such SOI substrates 12 are well known to those skilled in the art.
FIG. 1A depicts the illustrative SOI substrate 12 after an illustrative layer of insulating material 14 (e.g., a pad oxide layer) was formed above the active layer 12A. FIG. 1B depicts the substrate 12 after one or more etching processes were performed though a patterned etch mask, e.g., a patterned layer of photoresist, to remove the active layer 12A and the BOX layer 12B from above the non-FET region. As depicted, this process operation exposes the upper surface 13 of the bulk layer 12C in the non-FET region. At this point, various process operations may be performed to form the non-FET circuit element (not shown) in and above the bulk layer 12C in the non-FET region, and to form the FET device (not shown) in and above the active layer 12A in the FET region of the substrate 12. Unfortunately, using this manufacturing technique, there is a significant height difference, e.g., 10-200 nm (depending upon the particular application), between the upper surface 13 of the bulk layer 12C and the upper surface 12S of the active layer 12A. The existence of such significant changes in the topography of the overall substrate 12 can be problematic for many subsequent manufacturing operations that are performed to create the final integrated circuit problem. For example, such topography changes can make the formation of accurate patterned photoresist masks more challenging due to depth of focus issues caused by such topography changes. Additionally, such topography changes can make the formation of conductive contacts to both the FET devices and the non-FET element more challenging in that, due to the height difference 15, the overall height (or length) of the conductive contacts that contact the non-FET circuit element is greater than the conductive contacts that contact the FET device.
FIG. 1Cs depict a prior art technique that was employed in an effort to reduce or eliminate the topography problem noted above with respect to FIG. 1B. As shown in FIG. 1C, starting with the SOI substrate shown in FIG. 1B, a layer of undoped epi semiconductor material 16 was formed on the exposed upper surface 13 of the bulk layer 12C. The intent of this process was that the epi semiconductor material 16 would be formed in such a manner that its upper surface 16S would be substantially coplanar with the upper surface 12S of the active layer 12A. Unfortunately, during the epi growth process, the epi semiconductor material 16 also grows from the side surface 12X of the active layer 12A. As a result, it was frequently the case that simplistically depicted protrusions or irregularities 16X of the semiconductor material 16 would form at or near the interface between the semiconductor material 16 and the edge of the active layer 12A. The presence of such protrusions 16X required the performance of additional process operations to remove them (either partially or completely). In the case where the protrusions 16X could not be completely removed, their presence had a tendency to reduce the performance of the IC product formed on the substrate 12. Another problem with this approach is that the non-FET regions are typically very large and therefore increase the cost of production due to the requirement to deposit the epi semiconductor material 16 in these relatively large areas.
The present disclosure is directed to various methods of forming field effect transistors (FETs) and at least a portion of a non-FET circuit element on a semiconductor-on-insulator (SOI) substrate that may avoid, or at least reduce, the effects of one or more of the problems identified above.